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rda_cataloging_for_e-resource_originals_of_umass_dissertations_and_theses [2014/09/04 10:50]
kdion added advisor info
rda_cataloging_for_e-resource_originals_of_umass_dissertations_and_theses [2015/05/13 14:36] (current)
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 | 506 0_   | | Open access. ​ [Or 506 1_ Restricted to the UMass community.] ​                 | | 506 0_   | | Open access. ​ [Or 506 1_ Restricted to the UMass community.] ​                 |
 |          | |                                                                               | |          | |                                                                               |
-| 538      | | Available online in PDF format via Scholarworks at UMass Amherst.                                               ​| ​         | |                                                                               |+| 538      | | Available online in PDF format via Scholarworks at UMass Amherst ​             
 |          | |                                                                               | |          | |                                                                               |
-| 500      | | Degree in <program name> from the University of Massachusetts Amherst ​Department of <​department name> ​[NOTE:​ There must be a 710 access point for this department.] ​                       ​|+| 500      | | Degree in <program name> from the University of Massachusetts Amherst. ​       |
 |          | |                                                                               | |          | |                                                                               |
 | 504      | | Includes bibliographical references (pages <​nbr>​-<​nbr>​). ​                     | | 504      | | Includes bibliographical references (pages <​nbr>​-<​nbr>​). ​                     |
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 | 506 0_   | | Open access. ​                                                                      | | 506 0_   | | Open access. ​                                                                      |
 | 538      | | Available online in PDF format via Scholarworks at UMass Amherst. ​                                                   | | 538      | | Available online in PDF format via Scholarworks at UMass Amherst. ​                                                   |
-| 500      | | Degree in Electrical and Computer Engineering from the University of Massachusetts Amherst ​Department of Electrical & Computer Engineering.                                                  |+| 500      | | Degree in Electrical and Computer Engineering from the University of Massachusetts Amherst. ​                                                 |
 | 504      | | Includes bibliographical references (pages 333-352). ​                              | | 504      | | Includes bibliographical references (pages 333-352). ​                              |
 | 520 3_   | | In the era of multi-core computing, the push for creating true parallel applications that can run on individual CPUs is on the rise. Application of parallel discrete event simulation (PDES) to hardware design verification looks promising, given the complexity of today'​s hardware designs. Unfortunately,​ the challenges imposed by lack of inherent parallelism,​ suboptimal design partitioning,​ synchronization and communication overhead, and load balancing, render this approach largely ineffective. This thesis presents three techniques for accelerating simulation at three levels of abstraction namely, RTL, functional gate-level (zero-delay) and gate-level timing. We review contemporary solutions and then propose new ways of speeding up simulation at the three levels of abstraction. We demonstrate the effectiveness of the proposed approaches on several industrial hardware designs. ​                                                                                | | 520 3_   | | In the era of multi-core computing, the push for creating true parallel applications that can run on individual CPUs is on the rise. Application of parallel discrete event simulation (PDES) to hardware design verification looks promising, given the complexity of today'​s hardware designs. Unfortunately,​ the challenges imposed by lack of inherent parallelism,​ suboptimal design partitioning,​ synchronization and communication overhead, and load balancing, render this approach largely ineffective. This thesis presents three techniques for accelerating simulation at three levels of abstraction namely, RTL, functional gate-level (zero-delay) and gate-level timing. We review contemporary solutions and then propose new ways of speeding up simulation at the three levels of abstraction. We demonstrate the effectiveness of the proposed approaches on several industrial hardware designs. ​                                                                                |
rda_cataloging_for_e-resource_originals_of_umass_dissertations_and_theses.txt · Last modified: 2015/05/13 14:36 (external edit)
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